The present invention relates to data processors, and more particularly to a method and apparatus for configuring a data processing system after reset.
In order to place a data processing system in a known initial state, most data processing systems are equipped with a pin or other mechanism that causes the system to reset. As the processing system comes out of the reset condition, the address of a reset vector (reset exception vector) is fetched from a known location in memory. The address is then used to fetch and execute the reset exception routine. The reset exception routine typically includes a number of instructions that initialize the system and prepare it for execution of subsequent programming instructions.
In a processing system that includes a 32-bit address space, the reset vector would include one 32-bit word that is made up of four 8-bit bytes. The reset vector is fetched from a memory structure that may be of varying bit width. For example, a 32-bit wide memory structure, a 16-bit wide memory structure, or an 8-bit wide memory structure may be used to store the reset vector for a particular system. The type of memory structure that stores the reset vector will determine the memory operations necessary to fetch the four 8-bit bytes that comprise the reset vector.
One prior art technique for determining the memory configuration of the memory storing the reset vector includes additional pins on the processing system, where signals on the additional pins indicate the memory configuration. Additional pins add cost to the processing system and are therefore undesirable.
Another prior art technique for determining the memory configuration includes sampling a data bus of the processing system. The values determined from sampling the data bus indicate the particular memory configuration in which the reset vector was stored. Although this technique enables different memory structures to be supported in the processing system, external glue logic is required in order to drive the data bus to the particular values required to indicate the memory configuration being used. The external glue logic increases the cost of the overall processing system and may adversely affect functionality of the processing system as it induces additional parasitic effects and may also increase power consumption.
Another technique for determining the configuration of the memory storing the reset vector is to include non-volatile storage means in the processing system. The non-volatile storage means can then be used to store a value that indicates the memory configuration used in a particular system. Once again, although this allows for the use of various bit width memory structures in the processing system, the inclusion of non-volatile storage means can increase system costs as non-volatile storage means, such as electrically erasable programmable read-only memory, are complex and expensive to implement. In addition to the increased costs, non volatile storage means are often difficult to reprogram, thus making the ability to change between different memory configurations more difficult.
Other prior art systems assumed a specific external memory configuration and required the external memory to conform to the assumption. FIG. 1 illustrates a processor that includes a CPU and a memory controller. Three different memory configurations are also illustrated in FIG. 1, including 32-bit, 16-bit, and 8-bit configurations. The address data and control signals used by the memory controller to access each of the different potential memory structures are also illustrated.
If the system illustrated in FIG. 1 assumes that a memory structure with a 16-bit data bus is used to store the reset vector, two sequential read operations to addresses 0x00 (hexadecimal format) and 0x02 will be performed to retrieve the four bytes (T, U, V, and W) that make up the 32-bit reset vector. Although the execution of these two accesses work with respect to the 16-bit memory, similar attempts to load the address of the reset vector using the same assumptions fail with respect to the 32-bit and 8-bit memory structures.
With respect to 8-bit memory structure, only two read operations using two addresses are performed. While the memory controller will expect to receive 16-bits of data on the D[31:0] data lines for each read operation, the 8-bit memory will only drive the D[31:24] data lines. Therefore, only two of the four bytes that comprise the reset vector address will be retrieved from the 8-bit memory.
With respect to the 32-bit memory, the address line A[1] is ignored by the 32-bit memory. As such, the two sequential reads to 0x00 and 0x02 will result in duplicate reads of the 32-bit word stored at location 0x00 in the 32-bit memory. Although the 32-bit memory drives the entire reset vector address onto the data lines D[31:0], the memory controller assumes that only 16-bits of data will be received for each memory access on data lines D[31:16]. As such, the memory controller will interpret the results of the memory operations and arrive at an address that includes two copies of two of the four bytes that make up the reset vector address (VWVW) instead of the complete 4-byte address (TUVW).
Therefore, a need exists for a method and apparatus that enables a processing system to utilize various bit width memory structures without the need for additional pins, non-volatile storage locations, or data bus sampling in order to accurately determine the address of the reset vector when coming out of reset. In addition, it is desirable to have a method and apparatus that allows for configuration of various processing system parameters immediately out of reset such that subsequent operations utilize the configured parameters.